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Job Description
Structured overview of role & requirementsAbout This Role
Build and maintain UVM-based verification environments for DesignWare IP cores across protocols like USB, PCIe, Ethernet, and AMBA.
Develop test plans, write SystemVerilog testbenches, constrained-random tests, and coverage models to achieve verification closure.
Debug RTL and testbench issues with simulators, manage regressions, analyze coverage, and drive IP to signoff quality.
Minimum Requirements
Bachelor's or Master's in Electrical Engineering or Computer Engineering.
5+ years verification experience for IP cores or SoC designs if Bachelor's; 3+ years if Master's.
Strong SystemVerilog and UVM/VMM/OVM methodology experience.
Experience with simulators such as VCS, NC (Xcelium), or MTI (Questa).
Ideal Candidate Profile
Able to independently translate protocol specifications into comprehensive test plans and identify critical verification scenarios.
Proficient at debugging regressions, analyzing waveforms, and collaborating with design engineers to resolve issues efficiently.
Experienced working collaboratively in global teams and contributing to verification methodology improvements across broad IP portfolios.