Senior Staff Engineer Analog Mixed-Signal Verification

Develop advanced AI-based SystemVerilog Real Number Models (RNM) for analog/mixed-signal verification focused on accuracy and speed trade-offs.

Lead subsystem and full-chip (Analog on Top) AMS verification for automotive mixed-signal products, including developing test plans, checkers, assertions, and coverage solutions.

Drive verification efficiency by coordinating with Analog, RTL & DV teams, performing SoC power analysis, supporting post-silicon characterization, and mentoring junior engineers.

Experience required: Strong background in analog & mixed-signal verification including AMS test planning, SystemVerilog RNM modeling, and verification at subsystem and full-chip levels.

Proficient with analog design concepts like BGR, LDO, Buck-Boost regulators and EDA tools/simulators such as Cadence Virtuoso, Xcelium, APS/XPS or Synopsys VCS.

Ability to develop AMS verification environments incorporating spice netlists, checkers, assertions, coverage, and debugging AMS simulations.

Experience in scripting and automation using Python, Perl, and Shell; Work Experience Required: Not explicitly mentioned in the JD.

Proven expertise in automotive analog/mixed-signal product verification with working knowledge of behavioral model development and system-level validation.

Capable of handling dynamic project scope and mentoring junior engineers while integrating multiple functional teams for complex AMS verification.

Experienced with SoC-level power analysis and post-silicon validation support in a mixed-signal semiconductor environment.