Senior Staff Verification Engineer

Lead detailed simulation, verification, and validation of integrated circuits using System Verilog and UVM.

Develop and maintain comprehensive testbenches, UVM components (agents, scoreboards, environments), assertions, and functional coverage to ensure full verification space coverage.

Provide expert-level communication with cross-functional teams and customers, ensuring verification schedule adherence, issue resolution, and participation in design reviews and post-silicon validation.

Bachelor’s degree in Electrical Engineering or equivalent.

8+ years of experience in ASIC verification.

Proven expertise with UVM and/or System Verilog based verification methodologies.

Experience with source control, bug tracking, and release tools such as Jenkins, Git, and Jira.

Experienced in driving closure of verification metrics and identifying gaps in functional, power aware, and gate-level timing verification.

Capable of independently managing regression setups, debugging RTL and gate level netlists.

Skilled in high-level communication representing verification teams in customer interactions and design reviews.