Senior Staff AMS Design Verification Engineer

Lead design verification for analog & mixed signal integrated circuits to achieve first pass silicon success, ensuring performance, power, and timescale targets are met.

Develop and implement advanced verification strategies and reusable environments following object-oriented principles including UVM, and manage related activities such as planning, coverage, and debugging.

Provide technical leadership and mentoring to verification teams, coordinate cross-functional reviews, and contribute to analog verification strategy at management and customer levels.

Degree in electrical/electronics/computer engineering, computer science, or equivalent.

10+ years of experience in advanced verification methodologies for complex digital and mixed signal designs.

Expertise in SystemVerilog, UVM, analog/mixed signal verification tools (Cadence Virtuoso, xCelium, Incisive, vManager, IMC), and experience with analog schematic interpretation and RTL coding in Verilog.

Experience with scripting languages (UNIX shell, Perl, TCL); developing verification plans, testbenches, and debugging simulation results.

Seasoned verification leader capable of managing multi-site, multi-cultural teams and interfacing with customers and contractors effectively.

Strong technical background combining analog/mixed signal circuit knowledge with advanced verification methodologies and scripting skills.

Proven ability to drive strategic improvements, manage resources efficiently, and deliver high-quality results under tight schedules.