Applications Engineering, Sr Staff Engineer (Static Timing Analysis)
SynopsysMatch Score
Against your primary resumeLogin to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Protocol Intelligence
Data-driven signals on your job's competitivenessLog in to see why each signal reads the way it does.
Job Description
Structured overview of role & requirementsAbout This Role
Lead and drive adoption of Synopsys PrimeTime at customer sites from benchmarking to tape-out support for advanced node designs.
Deliver hands-on technical support during critical design phases resolving timing, signal integrity, and variation challenges directly with customer engineers.
Develop automation scripts, deliver training, and translate customer needs to R&D to influence product roadmap and improve timing closure workflows.
Minimum Requirements
Bachelor's degree in Electrical Engineering or equivalent; Master's degree acceptable with reduced experience requirement.
10+ years experience in ASIC/SoC design or EDA applications (8+ years with Master's).
Deep hands-on experience with Synopsys PrimeTime including timing analysis, constraint development, and sign-off flows.
Proficiency in TCL scripting for automation and methodology development within EDA tool environments.
Ideal Candidate Profile
Expert in static timing analysis with strong ability to diagnose complex timing issues quickly in high-pressure environments such as tape-out cycles.
Skilled at conducting and communicating competitive benchmarks demonstrating technical superiority and business value.
Experienced in building lasting trust with customer engineering and management teams as a credible technical advisor through direct field interaction.