DDR PHY Senior Lead Design Verification Engineer

Lead design verification efforts for DDR PHY IPs targeting next-generation SoCs for smartphones, tablets, and laptops.

Own the design verification (DV) test bench and related collateral including checkers, scoreboards, assertions, and functional coverage.

Collaborate with design, subsystem/SoC, and SVE teams for debugging, coverage closure, DSF, and post-silicon issue root cause analysis.

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years experience OR Master's with 5+ years OR PhD with 4+ years in Hardware Engineering or related work.

5+ years experience in complex IP design verification, specifically DDR PHY architecture and related protocols (DFI, Jedec standards).

Proficient in Verilog/System Verilog and UVM/OVM methodologies with strong functional verification, coverage, and debugging skills.

Work Experience Required: 5+ years design verification experience in DDR PHY or similar complex IPs.

Experienced in developing and owning DV test benches and verification plans for complex SoC IPs with thorough understanding of DDR PHY architecture and protocols.

Skilled in debugging regression failures and root cause analysis at IP and subsystem level, including collaboration for silicon bring-up and HW-SW debug.

Proficient with verification methodologies (UVM), scripting (Perl/Tcl preferred), and able to work closely with cross-functional design and system teams for quality sign-off.