Formal Verification Engineer

Own end-to-end formal verification of interconnect fabric, protocol bridges, and link-layer logic including property specification through proof convergence across multiple protocol domains.

Develop and execute formal verification test and coverage plans, create abstraction models, and generate/validate formal proofs to ensure design correctness.

Collaborate cross-functionally with architecture, RTL design, and physical design teams to enhance verification of complex features and maintain formal verification infrastructure and methodologies.

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.

Minimum 5 years of relevant experience in formal verification.

Proficiency with formal verification tools and methodologies including model checking and equivalence checking; strong knowledge of System Verilog, Verilog, logic, and microarchitecture fundamentals.

On-site presence required in Bangalore, India.

Deep expertise in formal methods with hands-on experience in abstraction modeling, simulation techniques, and convergence strategies across protocol verification.

Experienced working in cross-functional teams involving architecture, design, and software groups to address complex verification challenges.

Strong coding skills and growing ability to mentor junior engineers in formal verification processes and tool usage.