DDR Design Verification Staff Engineer
Qualcomm Incorporated (company site, opens in a new tab)11+ yrsBengaluruOn-siteDirect career pageEst. 35–55 LPA
Posted on 28 Sept
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Job description
Structured overview of role & requirements
About This Role
- Lead design verification for LPDDR/DDR IPs and subsystems, focusing on test plan creation, debugging, assertion writing, and coverage closure.
- Develop and maintain design verification infrastructure including integrating Verification IPs (VIPs).
- Collaborate with stakeholders to ensure high quality verification and program success.
Minimum Requirements
- Bachelor's degree or higher in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- 11+ years of Hardware Engineering or related work experience.
- Strong skills in Debug, UVM, System Verilog, test plans based on specs and standards.
- Experience with DDR/LPDDR technologies and relevant bus protocols (AHB/AXI/ACE/ACE-Lite).
Ideal Candidate Profile
- Experienced in digital design and design verification methodologies and tools, especially UVM and System Verilog.
- Comfortable navigating complex test benches, analyzing coverage, and debugging failures to identify root causes.
- Demonstrated ability to build and automate verification infrastructure for complex IP subsystems involving memory standards like DDR/LPDDR.