DDR Design Verification Staff Engineer
Qualcomm IncorporatedMatch Score
Against your primary resumeLogin to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Protocol Intelligence
Data-driven signals on your job's competitivenessLog in to see why each signal reads the way it does.
Job Description
Structured overview of role & requirementsAbout This Role
Lead design verification for LPDDR/DDR IPs and subsystems, focusing on test plan creation, debugging, assertion writing, and coverage closure.
Develop and maintain design verification infrastructure including integrating Verification IPs (VIPs).
Collaborate with stakeholders to ensure high quality verification and program success.
Minimum Requirements
Bachelor's degree or higher in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
11+ years of Hardware Engineering or related work experience.
Strong skills in Debug, UVM, System Verilog, test plans based on specs and standards.
Experience with DDR/LPDDR technologies and relevant bus protocols (AHB/AXI/ACE/ACE-Lite).
Ideal Candidate Profile
Experienced in digital design and design verification methodologies and tools, especially UVM and System Verilog.
Comfortable navigating complex test benches, analyzing coverage, and debugging failures to identify root causes.
Demonstrated ability to build and automate verification infrastructure for complex IP subsystems involving memory standards like DDR/LPDDR.