Principal Engineer, Design Verification Engineering

Lead end-to-end design verification for complex digital SoCs and subsystems, including microprocessor designs, AI/ML accelerators, and high-speed peripherals.

Formulate and implement verification strategies, methodologies, and architectures ensuring verification closure with functional and code coverage.

Collaborate with cross-functional teams (architecture, design, emulation, FPGA, software) to ensure pre-silicon readiness and full-system correctness.

B.Tech or M.Tech degree required.

12+ years of experience in digital pre-silicon verification with leadership in IP, subsystem, or SoC-level DV.

Proficient in Verilog/SystemVerilog, UVM-based testbench development, debugging, and methodology implementation.

Experience with NoC/interconnect verification, power-aware verification (UPF), formal verification, and protocol verification (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3).

Experienced in leading verification teams and driving cross-functional collaboration on complex SoC projects.

Deep technical expertise in scalable UVM testbench architecture and advanced verification methodologies including power analysis and formal techniques.

Exposure to processor-based systems (ARM, RISC-V, Tensilica) and accelerators with proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).