Senior Staff Design Verification Engineer
GlobalFoundries (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted on 28 Sept
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Job description
Structured overview of role & requirements
About This Role
- Own the development and maintenance of advanced UVM-based verification environments for complex SoC and subsystem-level designs.
- Drive verification planning, methodology, and coverage closure including debugging RTL, testbench, integration, and simulation failures.
- Mentor junior engineers and lead verification methodology improvements while collaborating across architecture, RTL, design, and system teams.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, or related discipline.
- Minimum 8 years of industry experience in digital design verification or SoC verification.
- Strong expertise in SystemVerilog, UVM methodologies, constrained-random verification, assertions (SVA), coverage-driven verification, and debugging.
- Experience verifying processors, memory subsystems, interconnects, complex SoC architectures, and proficiency with industry-standard simulators and scripting languages (Python, Perl, Tcl, Shell).
Ideal Candidate Profile
- Senior engineer with deep expertise in complex SoC verification environments and methodology development.
- Strong technical leadership demonstrated via mentoring and improving verification processes across multiple projects.
- Experienced in collaborating within global, cross-functional teams on semiconductor SoCs involving processor, memory, interconnect, and peripheral subsystems.