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Protocol Intelligence
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Job Description
Structured overview of role & requirementsAbout This Role
Own end-to-end formal verification of interconnect fabrics, protocol bridges, and link-layer logic using advanced formal methods.
Develop and execute formal verification test plans including property specification and proof convergence across multiple protocols.
Collaborate with architecture, design, and software teams to ensure high-quality and reliable silicon solutions.
Minimum Requirements
Bachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years experience OR Master's degree with 3+ years OR PhD with no prior experience.
Proficiency in formal verification tools and methodologies such as model checking and equivalence checking.
Strong knowledge of SystemVerilog, Verilog, and fundamentals of logic/microarchitecture.
Familiarity with abstraction modeling, Binary Decision Diagrams (BDD), and Data Flow Graphs (DFG).
Ideal Candidate Profile
Experienced in solving complex formal verification and architectural challenges in silicon design environments.
Able to collaborate effectively with cross-functional teams including architecture, RTL design, and physical implementation.
Skilled in advancing verification tools, methodologies, and technical documentation in high-tech engineering contexts.