Mixed- Signal Systems and Verification Engineer
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 EDA brand and Bengaluru location increase applicant density despite niche mixed-signal specialization.
Specialized mixed-signal and Cadence tooling expertise limits transferability across industries.
Many mandatory analog verification skills and Cadence tool experience create strict shortlisting filters.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and verify accurate analog behavioral models for analog/RF blocks using SystemVerilog.
Verify analog functionalities against design specifications by coding test benches, test scenarios, and assertions.
Integrate analog behavioral models with RTL and document modeling and verification results for formal review.
Minimum Requirements
Experience in developing and verifying real-numbered behavioral models in SystemVerilog.
Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
Basic understanding of AMS blocks such as filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc.
Work Experience Required: Not explicitly mentioned in the JD.
Ideal Candidate Profile
Hands-on experience with Cadence Virtuoso Schematic Composer and ADE and low power architecture.
Experience with Analog Assertion Based Verification and testbench development (strong plus).
Familiarity with scripting languages such as Perl or Python and FPGA prototyping experience is advantageous.