Mixed- Signal Systems and Verification Engineer
Candescent (company site, opens in a new tab)BengaluruOn-siteDirect career pageEst. 8–18 LPA
Posted on 25 Sept
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Job description
Structured overview of role & requirements
About This Role
- Develop and verify accurate analog behavioral models for analog/RF blocks using SystemVerilog.
- Verify analog functionalities against design specifications by coding test benches, test scenarios, and assertions.
- Integrate analog behavioral models with RTL and document modeling and verification results for formal review.
Minimum Requirements
- Experience in developing and verifying real-numbered behavioral models in SystemVerilog.
- Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
- Basic understanding of AMS blocks such as filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc.
- Work Experience Required: Not explicitly mentioned in the JD.
Ideal Candidate Profile
- Hands-on experience with Cadence Virtuoso Schematic Composer and ADE and low power architecture.
- Experience with Analog Assertion Based Verification and testbench development (strong plus).
- Familiarity with scripting languages such as Perl or Python and FPGA prototyping experience is advantageous.