ASIC Verification Engineer
Hewlett Packard Enterprise (HPE)Match Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand, mid-level (3+ yrs) and Bengaluru metro, though niche ASIC skills limit applicant density.
Specialized SystemVerilog/UVM and ASIC verification expertise limits transferability across industries.
Explicit 3+ years plus mandatory SystemVerilog/UVM, simulators and scripting make filters stringent.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and maintain ASIC verification environments using SystemVerilog and UVM methodologies.
Independently verify complex ASIC blocks and manage tape-out readiness through coverage and gate-level simulation.
Collaborate with design and software teams to debug, validate, and enhance verification flows and infrastructure automation.
Minimum Requirements
Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
3+ years of ASIC Verification experience.
Proficiency in SystemVerilog, UVM, constrained-random verification techniques, and scripting languages (Perl/Tcl preferred).
Onsite work expected at HPE office location.
Ideal Candidate Profile
Experienced in designing and executing full chip verification with strong functional and code coverage focus.
Comfortable working independently within established frameworks and collaborating cross-functionally with engineering teams.
Strong debugging and problem-solving skills with prior exposure to ASIC networking protocols (Ethernet experience is a plus).