Sr Lead Engineer - Post Si Validation
Qualcomm IncorporatedMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand and metro location but niche silicon-validation skills yield medium competition.
Highly domain-specific semiconductor validation skills limit transferability across industries.
Explicit years plus mandatory low-level silicon, debug, and kernel skills make shortlisting highly strict.
Job Description
Structured overview of role & requirementsAbout This Role
Lead Silicon Validation activities for Qualcomm Snapdragon SoC including bringing up SVE convex infrastructure and IST framework to enable VI content in production.
Own and execute SoC frequent regression suites considering design corner cases related to power and performance, including lab bench validations and support for SLT teams in debug and feature enablement.
Use silicon debug hooks to measure power, performance, coverage, and other KPIs and manage issue reporting and debugging with cross-functional teams.
Minimum Requirements
Bachelor's degree in Science, Engineering, or related field with 3+ years of ASIC design, verification, validation, or integration experience; OR Master's degree with 2+ years; OR PhD with 1+ year.
Strong knowledge of processor architecture including multicore/multiprocessor with SMP/MTE/heterogeneous cores.
Proficiency in C language for low-level programming, Assembly language, and understanding of OS/RTOS/Linux kernel internals including scheduling, locking, MMU/paging.
Experience with JTAG based debuggers, compilers/linkers, and software development life cycle; experience on emulation/pre-Si environment is a plus.
Ideal Candidate Profile
Experienced in working within complex SoC and ASIC environments, especially in silicon validation and hardware-software bring-up.
Capable of independently owning end-to-end regression and validation activities while collaborating effectively with cross-functional teams including IP validation and system validation engineers.
Knowledgeable about SoC architecture paradigms, power management, and silicon enablement software development, with a focus on performance and power optimization.