Senior Staff Engineer
Samsung Electronics Co., Ltd.Match Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand, generic senior title, and metro Bangalore increase applicant density.
Highly specialized semiconductor DV skills limit cross-industry transferability.
Explicit 7–10 years plus specialized UVM/SystemVerilog and protocol requirements create high filtering.
Job Description
Structured overview of role & requirementsAbout This Role
Own end-to-end design verification (DV) activities for IP including test plan creation, testbench development, and DV infrastructure.
Collaborate with cross-functional teams across multiple geographies to drive verification projects to completion.
Lead IP DV projects technically and through team guidance; execute debugging and leverage SoC architecture knowledge for DV signoffs.
Minimum Requirements
7 to 10 years of relevant work experience in design verification for SoC/Sub System/IP.
Strong expertise in verification tools and methodologies including UVM, SystemVerilog, CDV, MDV.
Must have domain expertise in one or more: AXI, PCIe, UCIe protocols.
B.Tech/B.E/M.Tech/M.E degree in a relevant field.
Ideal Candidate Profile
Experienced in independently driving IP design verification projects with hands-on execution and leadership abilities.
Comfortable working with hybrid testbenches involving SystemVerilog, SystemC, and Python for verification.
Capable of collaborating effectively with distributed teams and adapting to multi-geo coordination.