Senior Staff Engineer
Samsung Electronics (company site, opens in a new tab)7–10 yrsBengaluruOn-siteDirect career pageEst. 30–45 LPA
Posted on 24 Sept
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Job description
Structured overview of role & requirements
About This Role
- Own and independently lead IP design verification (DV) projects including testplan creation and testbench development.
- Collaborate with cross-functional teams across geographies to execute full verification cycle and achieve signoff.
- Focus on verification of SoC/Sub System/IP with strong domain expertise in AXI, PCIe, or UCIe protocols.
Minimum Requirements
- 7 to 10 years of experience in IP design verification, SoC, or subsystem DV.
- Must have hands-on experience with UVM, SystemVerilog, CDV/MDV verification methodologies.
- Degree requirement: B.Tech/B.E/M.Tech/M.E in a relevant engineering discipline.
- Expertise in developing testbenches and DV infrastructure for IPs with strong understanding of SoC architecture.
Ideal Candidate Profile
- Experienced in leading and technically guiding design verification teams while also executing hands-on debugging and testbench development.
- Strong verification domain expertise particularly in AXI, PCIe, and UCIe protocol IPs, with knowledge of hybrid testbenches (SystemVerilog, SystemC, Python) considered a plus.
- Comfortable working in a large, globally distributed R&D environment with multiple cross-functional collaborations.