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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 employer, metro location, and senior generic title increase competition despite niche DV skill requirements.
Highly specialized semiconductor DV and UVM/SystemVerilog skills limit cross-industry transferability.
Explicit 7–10 years requirement and mandatory verification tooling and protocol expertise make shortlisting highly strict.
Job Description
Structured overview of role & requirementsAbout This Role
Own and independently lead IP design verification (DV) projects including testplan creation and testbench development.
Collaborate with cross-functional teams across geographies to execute full verification cycle and achieve signoff.
Focus on verification of SoC/Sub System/IP with strong domain expertise in AXI, PCIe, or UCIe protocols.
Minimum Requirements
7 to 10 years of experience in IP design verification, SoC, or subsystem DV.
Must have hands-on experience with UVM, SystemVerilog, CDV/MDV verification methodologies.
Degree requirement: B.Tech/B.E/M.Tech/M.E in a relevant engineering discipline.
Expertise in developing testbenches and DV infrastructure for IPs with strong understanding of SoC architecture.
Ideal Candidate Profile
Experienced in leading and technically guiding design verification teams while also executing hands-on debugging and testbench development.
Strong verification domain expertise particularly in AXI, PCIe, and UCIe protocol IPs, with knowledge of hybrid testbenches (SystemVerilog, SystemC, Python) considered a plus.
Comfortable working in a large, globally distributed R&D environment with multiple cross-functional collaborations.