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Protocol Intelligence
Data-driven signals on your job's competitivenessStrong Tier-1 brand, mid-level (3-6 years) requirement, and metro location increase candidate competition density.
Highly specialized semiconductor EDA and STA expertise limits transferability across industries.
Mandatory EDA tools (ICC2/Innovus/PrimeTime), UNIX/scripting and 5+ years experience enforce strict filters.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and optimize place and route (PnR) flows for DRAM designs at advanced technology nodes, including hierarchical flows and UPF implementations.
Collaborate with EDA vendors to deploy and troubleshoot PnR tools, and customize EDA tools and in-house flows to enhance design team efficiency.
Lead implementation of AI-assisted and automated workflows for placement, routing, optimization, semi-automated floorplanning, and parasitic estimation.
Minimum Requirements
Bachelor’s degree in Electronics, Electrical, or Computer Engineering with 5+ years experience OR Master’s degree with 4+ years experience.
Hands-on experience with industry-standard place and route tools such as ICC2, Innovus, Primetime.
Strong scripting skills in TCL; familiarity with Perl and Python preferred.
Experience with defining STA constraints, corners, margins, and critical timing ECO & power closure at SoC level.
Ideal Candidate Profile
Experienced in physical design flows and methodologies for CMOS integrated circuits, specifically DRAM at advanced process nodes.
Skilled in collaborating across global design teams and with external EDA vendors to optimize production support flows.
Capable of leading AI-enabled automation and workflow deployments to improve productivity of design and layout teams.