Lead Verification Engineer
Cadence Design Systems, Inc. (company site, opens in a new tab)3+ yrsNoidaOn-siteDirect career pageEst. 12–20 LPA
Posted on 23 Sept
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Job description
Structured overview of role & requirements
About This Role
- Ownership of verification and quality assurance for Palladium emulation technology features and releases.
- Drive technical discussions including functional specification and test plan reviews for Palladium features.
- Mentor junior engineers and improve emulation validation and verification processes.
Minimum Requirements
- Degree in Electrical, Electronics, or Computer Science Engineering (B.Tech/BE/M.Tech/ME).
- 3+ years of relevant experience in functional verification and emulation domain.
- Proficient in HDLs (Verilog and/or VHDL), SystemVerilog, C++, UVM, and scripting for process automation.
- Experience with EDA tools, specifically Palladium emulation and debugging design/verification problems.
Ideal Candidate Profile
- Experienced in functional verification of complex digital systems such as SoCs using hardware verification languages.
- Strong technical communication skills for cross-functional collaboration and technical leadership.
- Demonstrated ability to mentor engineers and enforce quality standards for software/hardware releases in emulation technology.