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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand but niche EDA CAD skills and mid-level experience make competition moderate.
Highly specialized EDA and STA skills limit transferability across industries.
Explicit 5+ years, mandatory PnR/STA tool expertise and scripting create highly strict filters.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and optimize place and route (PnR) flows for advanced DRAM designs at leading-edge process nodes.
Collaborate with global design teams and EDA vendors to deploy and customize PnR tools, troubleshoot issues, and improve design team efficiency.
Lead implementation of AI-assisted and automated workflows for placement, routing, floorplanning, and parasitic estimation to accelerate design optimization.
Minimum Requirements
Bachelor’s degree in Electronics, Electrical, or Computer Engineering with 5+ years experience OR Master’s degree with 4+ years experience.
Strong hands-on experience with industry-standard place and route tools such as ICC2, Innovus, and Primetime.
Proficient in UNIX and scripting languages including TCL; familiarity with Perl and Python preferred.
Work Experience Required: 4-5+ years in relevant CAD/EDA/physical design engineering roles.
Ideal Candidate Profile
Experienced in advanced CMOS layout design flows including hierarchical flow, UPF, and process-specific customizations targeting DRAM designs.
Strong understanding of static timing analysis (STA) constraints, timing corners, margins, and signoff-level timing closure (ECO) at SoC scale.
Able to lead the adoption of AI-enabled and automated methodologies within PnR flows to improve productivity and design quality.