Senior Lead Verification Engineer
Qualcomm IncorporatedMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand plus mid-level specialized SoC verification role drives moderate competition.
SoC verification expertise is highly specialized and not easily transferable across industries.
Explicit 5–8 years and mandatory UVM/SystemVerilog, protocols, and tools make shortlisting highly strict.
Job Description
Structured overview of role & requirementsAbout This Role
Own and develop SoC design verification environments and testbenches at SoC, subsystem, and IP/core levels.
Lead complex SoC and subsystem verification including assertion development, debugging, and execution of verification methodologies.
Work on next-generation mobile and compute SoCs addressing system-level verification challenges and power-aware simulation methodologies.
Minimum Requirements
5 to 8 years of hands-on experience in SoC Design Verification.
Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field with 3+ years experience; or Master's degree with 2+ years; or PhD with 1+ year experience.
Strong proficiency in Verilog, System-Verilog, UVM, SVA, and industry-standard verification flows.
Experience with SoC architectures, boot flows, CPU architectures (RISC-V/ARM), power management, and protocols such as PCIe Gen5/6, USB 3.x/4, LPDDR4/5, QUP, eMMC, SD, UFS.
Ideal Candidate Profile
Experienced in SoC-level testbench architecture, test development, and test plan creation with strong root-cause analysis skills.
Skilled in scripting languages (Python, Perl, TCL, Bash) and waveform debugging tools like Verdi for automation and in-depth debugging.
Familiarity with power-aware verification methodologies, gate-level simulation, and broad system-level verification challenges associated with mobile and compute SoCs.