Senior Lead Verification Engineer
Qualcomm Incorporated (company site, opens in a new tab)5–8 yrsNoidaOn-siteDirect career pageEst. 20–40 LPA
Posted on 22 Sept
Reach people at Qualcomm Incorporated
People at this company you can reach
Log in to see who works here
Create a free account or log in to see the people at Qualcomm Incorporated you could write to:
- Recruiters & HR
- People in this function
- Work addresses
Your match
Against your primary resume
Log in to see your match score
Create a free account or log in to unlock your CV match score across:
- Role fit
- Experience
- Industry relevance
Protocol Intelligence
How competitive this role is
Competition
Background fit
Strictness
Log in to see why each signal reads the way it does.
Job description
Structured overview of role & requirements
About This Role
- Own and develop SoC design verification environments and testbenches at SoC, subsystem, and IP/core levels.
- Lead complex SoC and subsystem verification including assertion development, debugging, and execution of verification methodologies.
- Work on next-generation mobile and compute SoCs addressing system-level verification challenges and power-aware simulation methodologies.
Minimum Requirements
- 5 to 8 years of hands-on experience in SoC Design Verification.
- Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field with 3+ years experience; or Master's degree with 2+ years; or PhD with 1+ year experience.
- Strong proficiency in Verilog, System-Verilog, UVM, SVA, and industry-standard verification flows.
- Experience with SoC architectures, boot flows, CPU architectures (RISC-V/ARM), power management, and protocols such as PCIe Gen5/6, USB 3.x/4, LPDDR4/5, QUP, eMMC, SD, UFS.
Ideal Candidate Profile
- Experienced in SoC-level testbench architecture, test development, and test plan creation with strong root-cause analysis skills.
- Skilled in scripting languages (Python, Perl, TCL, Bash) and waveform debugging tools like Verdi for automation and in-depth debugging.
- Familiarity with power-aware verification methodologies, gate-level simulation, and broad system-level verification challenges associated with mobile and compute SoCs.