Principal Engineer, Design Verification Engineering
Analog Devices, Inc.Match Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 employer and Bangalore metro increase applicant density despite niche verification specialization and senior level.
Highly specialized semiconductor DV skills limit transferability across industries.
Explicit 12+ years requirement plus mandatory SystemVerilog/UVM/formal and NoC/protocol expertise tightens screening.
Job Description
Structured overview of role & requirementsAbout This Role
Lead end-to-end design verification of complex digital SoCs and subsystems, including microprocessor-based designs, AI/ML accelerators, and high-speed peripherals.
Formulate and execute verification strategies, define verification architecture, flows, and methodologies to achieve verification closure with functional and code coverage at block, subsystem, and SoC levels.
Collaborate across architecture, design, emulation, FPGA, firmware, and system teams to ensure comprehensive pre-silicon and post-silicon validation readiness.
Minimum Requirements
B.Tech or M.Tech degree.
12+ years of experience in digital pre-silicon verification with leadership across IP, subsystem, or SoC level design verification.
Expertise in Verilog/SystemVerilog, UVM-based testbench development, formal verification, low and high-speed interface protocols (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3).
Experience with power-aware verification (UPF), test planning, constrained-random verification, assertions, processor-based systems (ARM, RISC-V, Tensilica), C/C++, SystemC, and scripting (Python/TCL/Shell).
Ideal Candidate Profile
Experienced verification leader capable of driving scalable verification architectures and methodologies for large integrated SoC products.
Strong cross-functional collaborator comfortable working with architecture, design, emulation, FPGA, and system teams globally to synchronize verification efforts.
Deep domain expertise in SoC verification especially involving AI/ML accelerators, high-speed interfaces, and power-aware designs ensuring verification innovation and quality.