Post Silicon Validation -Sr/Lead/Staff Engineer
Qualcomm IncorporatedMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand, mid-level generalist role, metro location yield high applicant competition.
Highly specialized silicon post-silicon validation and embedded bring-up limits cross-industry transferability.
Mandatory 6+ years plus specific embedded, emulation, and tooling requirements make filtering strict.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and execute validation and integration tests for Multimedia-IP blocks in Silicon to ensure high quality and performance.
Collaborate with system architects, designers, firmware, and software engineers to gather requirements, develop low-level firmware/drivers in C/C++, and debug hardware and software issues.
Lead device-level and system-level verification, validation, and debugging activities using hardware platforms and emulation environments.
Minimum Requirements
Bachelor's degree or higher in Electronics, Computer Science, Electrical Engineering, or related field.
6+ years of experience in Systems, Debug, Integration Engineering, or related roles involving ASIC design, validation, or embedded software development.
Proficiency in C, C++, Python, Java, shell scripting, version control tools, and RTOS with experience using in-circuit emulation/debug tools.
Experience with Multimedia/Peripheral IP validation (USB/UART/UFS/PCIe), ARM cores, low-level HW interfaces, high-speed interfaces, signal integrity, and embedded software/driver development.
Ideal Candidate Profile
Experienced in embedded software development and hardware bring-up, especially ARM-based SoCs and emulation/debug environments.
Skilled in testing and debugging high-speed interfaces related to multimedia and imaging hardware, with knowledge of hardware lifecycle and digital IC architecture.
Experienced in lab test equipment usage (oscilloscopes, logic analyzers), JTAG debugging, scripting for automation, and familiar with low power design, machine learning tools, and partial knowledge of HDL/FPGA design.