Senior Design Verification Engineer
Analog Devices, Inc.Match Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand, mid-level (4–8 yrs), and metro Hyderabad increase candidate competition.
Specialized SoC verification, SystemVerilog/UVM, and automotive safety skills limit cross-industry transferability.
Explicit 4–8 years and mandated SystemVerilog/UVM and SoC verification skills create strict screening.
Job Description
Structured overview of role & requirementsAbout This Role
Lead verification planning and execution for next-generation automotive connectivity SoCs based on E2B technology.
Develop and maintain advanced SystemVerilog/UVM verification environments including firmware-driven scenarios and C DPI integration.
Collaborate cross-functionally to ensure robust verification coverage, support post-silicon validation, and mentor junior engineers.
Minimum Requirements
4–8 years of relevant digital or mixed-signal IC verification experience, including SoC verification with embedded processors.
Expert-level knowledge of SystemVerilog and UVM verification methodologies.
Proficiency in developing C/SystemVerilog DPI components and firmware-driven verification.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
Ideal Candidate Profile
Experienced in complex SoC verification involving embedded processors, memories, communication subsystems, and security features, preferably in automotive contexts.
Demonstrates strong debugging skills across RTL, UVM testbenches, embedded software, and system-level environments with an ability to lead verification independently.
Familiar with verification methodologies including coverage-driven verification, fault injection, and functional safety processes aligned with ISO 26262.