Design Verification Engineer
Analog Devices, Inc.Match Score
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Requires specialized SystemVerilog/UVM and SoC verification skills, limiting cross-industry transferability.
Explicit 2–4 year requirement plus mandatory SystemVerilog/UVM and SoC verification skills.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and maintain SystemVerilog/UVM verification environments for next-generation automotive connectivity SoCs based on E2B technology.
Verify complex SoC functionalities including embedded processors, communication interfaces, security functions, and mixed-signal components ensuring designs meet functional, quality, and reliability requirements before tape-out.
Collaborate cross-functionally with design, architecture, firmware, functional safety, and validation teams; analyze coverage, execute regressions, debug hardware-software interactions, and contribute to functional safety verification activities.
Minimum Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related technical field.
2–4 years of relevant experience in digital design verification with SystemVerilog/UVM testbench development.
Proficiency in SystemVerilog and UVM including testbench development, constrained-random and directed testing, functional and code coverage, and assertion-based verification.
Experience with C programming and DPI integration; knowledge of EDA simulation and debugging tools; experience verifying communication interfaces such as SPI, I2C, or UART.
Ideal Candidate Profile
Experienced with processor-based SoC verification including embedded processors (RISC-V or ARM) and firmware-driven verification.
Familiarity with automotive connectivity technologies, in-vehicle networking, E2B technology, and automotive functional safety/ISO 26262 verification processes.
Comfortable working in cross-functional teams on complex SoCs involving mixed-signal components, safety features, and regression automation in a moderately supervised environment.