Match Score
Against your primary resumeLogin to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 brand and Bangalore metro raise competition, but niche ASIC verification skills and SV/UVM requirement reduce applicant density.
Highly specialized ASIC verification skills (SystemVerilog/UVM/Formal) limit cross-industry transferability.
Requires explicit 3+ years and mandatory SystemVerilog/UVM, formal, and scripting skills, making filters strict.
Job Description
Structured overview of role & requirementsAbout This Role
Own end-to-end validation of clocking structures in Tegra automotive and datacenter ASIC products including test plan development, automation, coverage, execution, bug management, and productization.
Develop scalable verification solutions that manage complex clock and reset designs across multiple platforms using industry-standard tools and methodologies.
Collaborate closely with clocks architecture and design teams and coordinate with internal/external teams across time zones.
Minimum Requirements
Bachelor's or Master's degree in EE/ECE or equivalent experience.
3+ years of relevant industry work experience in ASIC verification.
Expertise in System Verilog, UVM, constraint random verification, formal verification, coverage metrics, and verification tools.
Strong coding skills in System Verilog, scripting languages (Perl, Python), and C++ required.
Ideal Candidate Profile
Experienced in block-level and system-level verification with a strong understanding of logic design and architecture.
Demonstrated ability to implement comprehensive test plans for pre-silicon platforms.
Able to work effectively across multiple teams and time zones in a complex product development environment.