Senior Staff Engineer, CAD & Methodology
Renesas Electronics CorporationMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessNiche semiconductor CAD skills and seniority reduce applicant density, but metro location and general Senior Engineer title increase competition.
Role requires specialized EDA, PDK, and tapeout experience, making cross-industry transferability low.
Explicit 10+ years plus mandatory EDA, PDK, and scripting experience makes screening highly stringent.
Job Description
Structured overview of role & requirementsAbout This Role
Develop, maintain, and release reference flows for Synthesis, STA, Place & Route, and Signoff to enable efficient and high-quality RTL-to-GDSII implementation.
Build and deploy automation solutions improving productivity including setup generation, QoR checks, report parsing, ECO automation, and deliverable packaging.
Drive methodology standardization, tool qualification, and provide technical support through tapeout by collaborating with physical design teams, EDA vendors, IT, and foundry partners.
Minimum Requirements
10+ years of experience in Physical Design CAD, Design Methodology, or Backend Design Automation.
Bachelor's or Master’s degree in Electronics or Electrical Engineering.
Strong familiarity with industry-standard EDA tools from Synopsys, Cadence, and/or Siemens.
Proficiency in scripting languages such as Tcl, Python, Shell, or Perl.
Ideal Candidate Profile
Experienced in developing CAD automation and methodology for backend physical design teams, particularly at advanced technology nodes (7nm and below).
Comfortable working across multiple functions including Physical Design, Timing, Signoff, EDA vendors, and IT infrastructure to drive tool deployment and flow improvements.
Proficient with flow validation, compute farm environments, Linux, Git, and CI/CD frameworks to support scalable design automation solutions.