Senior/Staff Engineer, Design Verification
Renesas Electronics CorporationMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessNiche SoC verification skills reduce competition despite mid-level experience and Bangalore location.
Highly domain-specific SoC verification skills limit cross-industry transferability.
Explicit 5-12 years, mandatory UVM/SystemVerilog, and EDA tool experience make filters strict.
Job Description
Structured overview of role & requirementsAbout This Role
Own end-to-end verification execution for complex digital IPs and subsystems from specification to sign-off ensuring first-pass silicon success.
Define and drive IP-level verification strategies including test plans, coverage models, and closure using metric-driven verification and AI/ML-assisted techniques.
Develop scalable UVM-based verification environments, advanced checkers, and collaborate across Architecture, RTL, Emulation, and SoC teams for high-quality, reusable IP delivery.
Minimum Requirements
5-12 years of experience in SoC Verification domain with working knowledge of industry-standard EDA toolkits.
Bachelor’s or Master’s degree in Electronics Engineering.
Strong expertise in UVM-based testbench architecture and development; proficiency in SystemVerilog, UVM, SVA, directed and constrained-random verification methodologies.
Experience debugging complex designs in simulation, emulation, and post-silicon environments; working knowledge of C/C++ and Shell scripting.
Ideal Candidate Profile
Experienced in metric-driven verification with coverage closure capabilities and advanced verification methodologies including AI/ML-assisted verification.
Demonstrated ability to lead verification strategy, environment architecture, and closure efforts for complex digital IP or subsystem verification.
Familiarity or experience with advanced techniques such as formal verification, scripting (Python, Perl, TCL), and working with high-speed or complex IPs such as H.264, security, or safety-critical blocks.