Senior/Staff Engineer, Design Verification
Renesas Electronics CorporationMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessMetro Bangalore role at a recognized semiconductor firm but highly specialized UVM/SystemVerilog skills limit applicant pool.
Role demands SoC verification and EDA tool expertise, restricting transferability across industries.
Requires explicit 2–8 years plus mandatory UVM/SystemVerilog and EDA expertise, making filters highly rigid.
Job Description
Structured overview of role & requirementsAbout This Role
Own end-to-end verification execution for complex digital IPs and subsystems, driving strategies from specification to sign-off.
Develop and lead scalable UVM-based verification environments and apply AI/ML-assisted techniques to accelerate coverage and optimize regressions.
Collaborate with multiple teams to ensure IP integration quality, mentor junior engineers, and support post-silicon debug and gate-level simulation as needed.
Minimum Requirements
Bachelor’s or master’s degree in Electronics Engineering.
2 - 8 years of experience in SoC Verification with knowledge of industry-standard EDA tools.
Strong expertise in UVM-based testbench architecture, SystemVerilog, assertions (SVA), and verification best practices.
Proficiency in Verilog/SystemVerilog and working knowledge of C/C++ and Shell scripting.
Ideal Candidate Profile
Experienced with metric-driven verification including functional and code coverage closure and debugging in simulation, emulation, and post-silicon environments.
Familiarity with AI/ML-based verification tools for stimulus optimization and coverage acceleration, as well as scripting in Python, Perl, or TCL for automation.
Exposure to complex/high-speed IPs (e.g., H.264) and knowledge of security, debug, or safety-critical domains.