Senior Staff / Staff Digital Verification Engineer
Renesas Electronics CorporationMatch Score
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Protocol Intelligence
Data-driven signals on your job's competitivenessTier-1 semicon brand, metro location, and mid-seniority increase competition despite niche UVM skills.
Specialized semiconductor UVM/SystemVerilog and RTL verification skills have low cross-industry transferability.
Explicit 6–14 years plus mandatory UVM/SystemVerilog and verification tooling creates stringent filtering.
Job Description
Structured overview of role & requirementsAbout This Role
Develop and maintain UVM-based verification environments, including test benches, test cases, and coverage models for complex IP and SoC designs.
Analyze specifications to define verification plans, execute verification scenarios, and debug RTL issues collaboratively with design, architecture, and firmware teams.
Run regressions daily, monitor coverage metrics, perform root-cause analysis of failures, and contribute to advancing verification methodologies and automation; mentor junior engineers and participate in design and verification reviews.
Minimum Requirements
6 to 14 years of experience in Digital Verification using System Verilog and UVM methodology.
Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or related discipline.
Strong expertise in System Verilog, UVM, constrained-random verification, and proficiency in verification tools (simulators, coverage tools, regression management) and scripting (Python/Perl/Tcl).
On-site full-time role based in Hyderabad, India.
Ideal Candidate Profile
Experienced in semiconductor product development, preferably for automotive, industrial, or embedded systems domains.
Strong understanding of computer architecture including memory hierarchies, bus protocols, and high-performance compute subsystems.
Capable of collaborating effectively in cross-functional, multicultural teams with strong communication skills and able to support external teams, including business travel when required.