Senior Engineer - Frontend CAD
Ericsson (company site, opens in a new tab)10+ yrsBengaluruOn-siteDirect career pageEst. 30–45 LPA
Posted on 17 Sept
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Job description
Structured overview of role & requirements
About This Role
- Shape and lead the development and verification of front-end CAD methodologies, DV flows, and infrastructure for ASIC IP and SoC development.
- Drive optimization and innovation of methodologies and EDA workflows across a global silicon engineering community, including AI/ML-driven design automation.
- Collaborate with design, verification, test, and manufacturing teams to improve silicon quality and verification productivity through scalable, long-term solutions.
Minimum Requirements
- 10+ years of experience in ASIC design verification.
- Proficiency in SystemVerilog, UVM, and scripting languages such as Python, Perl, bash, or csh.
- Strong knowledge of front-end verification tools including Verilog simulators, verification linters, CDC checkers, and formal verification tools.
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field from recognized and accredited institutions.
Ideal Candidate Profile
- Demonstrated ability to lead complex front-end DV tools and flows development in a multi-site global environment.
- Experience applying or willingness to apply AI/ML techniques to silicon design and verification flows for innovation and process improvements.
- Skilled in identifying and solving inefficiencies in verification methodologies and driving adoption of best practices across IP/ASIC/SoC verification contexts.