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Niche Chisel/formal verification skills limit applicants despite metro location and mid-level seniority.
Highly domain-specific semiconductor formal verification skills limit transferability across industries.
Explicit 7+ years and mandatory Chisel/Scala/formal verification tools imply strict filtering of candidates.
Develop and implement formal verification plans and formal properties for complex digital designs including RISC-V processors using Chisel/Scala.
Utilize formal verification tools to prove design correctness, uncover issues, and collaborate with design engineers to provide verification feedback.
Develop verification environments and improve formal verification efficiency including formal flows, functional coverage, and constrained-random verification strategies.
7+ years of hands-on experience in formal verification of digital hardware designs.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Proficiency in Scala programming and experience with Chisel hardware description language.
Experience with formal verification methodologies and tools, including assertion-based verification and TCL scripting.
Experienced in formal verification of RISC-V based or complex digital hardware IP blocks using Chisel/Scala.
Skilled in developing formal verification environments and improving verification flows using formal methods and constrained-random verification adapted for Chisel.
Able to analyze verification results critically and collaborate cross-functionally with design teams to resolve issues.