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NXP Tier-1 brand and Bengaluru metro increase applicants, but niche UVM/SystemVerilog expertise limits competition.
UVM/SystemVerilog IP verification is highly domain-specific and not easily transferable.
Explicit 7+ years plus mandatory UVM/SystemVerilog and verification methodology requirements create strict filters.
Own pre-silicon verification of IP modules or IP subsystems including defining and executing verification plans based on multiple requirement sources.
Architect, develop, debug, and operate UVM-based verification environments for RTL simulation covering a range of model types including power aware RTL, gate level, FPGA, and Emulation platforms.
Create and maintain test cases and verification stimuli, perform simulations, debug, run regression suites, and analyze code and functional coverage metrics.
Bachelor's degree in Electrical Engineering or Computer Science mandatory.
Minimum 7 years of experience in IP or Sub-System verification.
Proficient in UVM methodology, Verilog, SystemVerilog, and scripting languages (Shell mandatory, Perl/TCL/Python a plus).
Work Experience Required: 7+ years in IP/Sub-System verification with strong skills in testbench development and Metric Driven Verification.
Experienced in working across hardware, firmware, software, architectural, and system engineering teams to ensure comprehensive verification.
Demonstrated ability in directed and constrained random methodologies and formal verification concepts including assertions.
Track record of debugging pre- and post-silicon design issues across simulation and hardware test benches in complex SoC environments.