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Tier-1 employer and metro location but highly niche emulation/IP skills reduce applicant density.
Highly specialized semiconductor emulation and IP verification skills are not easily transferable across industries.
Explicit 15+ years and mandatory Zebu, PCIe/DDR/IP verification expertise create strict screening filters.
Own the alignment and enhancement of Zebu emulation IP capabilities to meet verification needs for PCIe, DDR, and Ethernet controllers and PHYs across functional and performance domains.
Define and validate technical requirements and test plans for emulation and design IP, ensuring full coverage of real-world and corner cases to improve silicon success.
Lead cross-functional global teams to standardize verification methodology and mentor engineers on emulation strategies and IP verification techniques.
15+ years of hands-on experience in emulation, IP verification, or ASIC digital design.
Deep expertise in PCIe and DDR protocols including verification strategies and standards compliance.
Extensive experience with Zebu or similar emulation platforms focused on IP-level verification and system integration.
Work Experience Required: 15+ years. Notice period: Not explicitly mentioned in the JD.
Demonstrated ability to detect critical corner cases early and devise actionable verification improvements based on data and real-world scenarios.
Experience operating in global, matrixed environments with strong communication skills to align IP and design verification teams.
Proven track record in driving emulation IP roadmap, evangelizing best practices, and mentoring engineers on verification as a structured product.