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Specialized EDA skills reduce applicant pool, but metro location and mid-level experience increase competition.
Strong EDA, RTL, HDL, and synthesis specialization limits cross-industry transferability.
Explicit 4-7 years plus mandatory HDL, synthesis, EDA tool, and scripting skills enforce strict shortlisting.
Own and address issues related to synthesis flows including Logical Equivalence Checking (LEC) and Constraint Logic Programming (CLP).
Function as an individual contributor coordinating with cross-geographic teams to resolve synthesis-related problems.
Utilize EDA tools to debug design issues within synthesis and verification processes.
4-7 years of experience in relevant roles involving synthesis, LEC, and CLP.
Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Science Engineering from a reputed institute.
Mandatory skills: strong understanding of HDLs (Verilog, SystemVerilog, and/or VHDL), RTL design and synthesis concepts, and process automation using PERL or Tcl scripting.
Good working knowledge of EDA tools (e.g., Cadence) focusing on debugging design issues.
Experienced in synthesis engagement with a solid grasp of low-power and power optimization concepts (leakage and dynamic).
Capable of functioning autonomously while effectively collaborating across teams and geographies.
Strong analytical and problem-solving abilities with practical experience in automating processes related to synthesis and design debugging.