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Tier-1 EDA employer in Bangalore but niche EDA skills and seniority limit applicant pool.
Highly domain-specific EDA and ASIC timing skills limit cross-industry transferability.
Requires specialized EDA experience, HDL, scripting, and node-level timing closure expertise, making filters strict.
Own product engineering for Genus Synthesis Solution focusing on optimizing Power, Performance & Area (PPA) for latest digital ASICs.
Verify new feature correctness, conduct experiments for optimal synthesis solutions bridging logic synthesis and place and route.
Provide primary support interface between R&D and customers, ensuring seamless interoperability with other digital logic tools and documenting product requirements.
Experience working with Cadence tools in design, synthesis, physical design, and timing closure at 20nm or below nodes.
Automation skills with Perl, Tcl, and shell scripting mandatory.
Knowledge of HDL (Verilog or System Verilog) preferred.
Degree requirement: BE/BTech/ME/MS/MTech or equivalent.
Experienced in digital implementation and synthesis within EDA industry, especially at 28nm or below foundry process nodes.
Strong logical and physical design troubleshooting skills with ability to perform root-cause analysis and provide actionable feedback to R&D.
Experienced in interfacing with customers and field engineers, supporting complex tools like Genus and Innovus in a product engineering or application engineering role.