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Niche EDA and Genus expertise limits applicant pool despite Bangalore metro.
Highly specialized semiconductor and EDA skills make cross-industry transfers unlikely.
Multiple mandatory EDA, synthesis, timing-closure, and scripting skills create strict filtering.
Own product engineering for Genus Synthesis Solution to optimize power, performance & area (PPA) for advanced digital ASICs.
Develop and verify new logic synthesis features, perform experiments to determine optimal solutions, and solve challenges in physical-aware synthesis bridging synthesis and place & route.
Provide first line support between R&D, Cadence field engineers, and customers; ensure interoperability of Genus with other Cadence tools; gather and document product requirements from stakeholders.
Experience in digital implementation, EDA tools, and synthesis with emphasis on Cadence products, preferably Genus and Innovus.
Knowledge of logic design, timing closure, physical design, formal verification, and low power design at 28nm node or below.
Proficiency in Perl, Tcl, shell scripting; familiarity with HDL (Verilog or System Verilog).
Education: BE/BTech/ME/MS/MTech or equivalent. Work Experience Required: Not explicitly mentioned in the JD.
Experienced in advanced digital IC implementation flow with expertise in synthesis and timing closure at advanced nodes (20nm or below).
Skilled in root-cause analysis and debugging of complex timing, logical, and physical design issues.
Capable of integrating customer feedback into product enhancements and supporting seamless tool interoperability within Cadence’s software ecosystem.