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Tier-1 brand and metro location but highly specialized EDA verification skillset reduces applicant density.
Highly domain-specific semiconductor verification expertise limits transferability across industries.
Requires explicit 6–10 years and specialized UVM/SystemVerilog and EDA tool expertise, making filters stringent.
Own validation and compliance of AI-generated verification artifacts within semiconductor RTL verification workflows including UVM testbenches, assertions, and coverage.
Investigate and resolve complex customer verification issues involving simulation failures, assertion violations, and coverage regressions.
Develop and maintain benchmark datasets and validation suites for AI model qualification, and collaborate with AI engineers to improve accuracy and reduce errors in AI-assisted verification solutions.
6–10 years of semiconductor verification experience with proven skills in UVM-based verification environments.
Strong knowledge of SystemVerilog, UVM, RTL Verification, Functional and Code Coverage, and Assertion-Based Verification (SVA).
Proficiency in debugging simulation failures, assertion violations, and complex testbench issues.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Deep expertise in semiconductor verification methodologies with hands-on experience in UVM and RTL/IP/subsystem verification.
Experienced in cross-functional collaboration involving engineering teams, AI specialists, and customers to ensure AI verification outputs are technically accurate and workflow-compliant.
Skilled at integrating AI-driven workflows with traditional EDA tools and improving verification automation and productivity through AI-assisted methods.