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Tier-1 EDA brand and Bangalore metro increase applicant density despite specialized verification niche.
Requires deep UPF, SystemVerilog, and EDA tool expertise, limiting cross-industry transferability.
Explicit 8–12 years, deep UPF and tool requirements, and customer-facing applications expertise make filters strict.
Lead technical deployment and implementation of power-aware simulation flows using VCS NLP at key semiconductor customer sites.
Debug and resolve complex low-power verification issues involving UPF modeling, power state transitions, retention logic, isolation strategies, and multi-domain power scenarios.
Act as a liaison between customers and Synopsys R&D to translate verification challenges into product requirements and influence the VCS NLP roadmap.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
8 to 12 years of experience in product engineering, applications engineering, or ASIC/SoC verification focused on low-power methodologies.
Deep expertise in IEEE 1801 (UPF) concepts including power domains, power state tables, retention strategies, isolation, level shifters, and power sequencing.
Strong proficiency in SystemVerilog, UVM, assertions (SVA), coverage-driven verification, RTL simulation flows; experience with Synopsys VCS or equivalent tools is a plus.
Experienced in handling critical, high-pressure low-power verification issues during tapeouts with clear root cause analysis and communication.
Able to distinguish and explain differences between UPF syntax errors and methodology gaps to technical leads to enable progress.
Skilled at converting complex customer technical challenges into clear, prioritized product requirements to guide R&D developments.