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Niche AMS/EDA skills reduce pool, but metro location and mid-level requirement increase competition.
Highly domain-specific EDA and AMS verification skills limit cross-industry transferability.
Explicit 3–5 years plus mandatory Cadence, SKILL, Python and AMS signoff skills increase filter strictness.
Develop and maintain automated verification workflows and methodology solutions for analog and mixed-signal (AMS) design teams using Cadence Virtuoso, Spectre/APS, and related platforms.
Build and deploy scalable automation frameworks (AC/DC/transient, noise, linearity, matching, corner/Monte Carlo coverage) to improve engineering productivity and enable design signoff.
Partner with design, CAD, PDK, and software teams to drive methodology adoption, provide technical support, and deliver training materials and reporting infrastructure for design signoff.
M.Tech/M.E./M.S. in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
3-5 years of experience in AMS methodology, CAD engineering, EDA applications engineering, or automation development.
Strong software development skills in Python and at least one of SKILL, Tcl, or Perl.
Experience with Cadence Virtuoso, Spectre/APS, and familiarity with design data management systems like Perforce, DesignSync, or Git.
Experienced engineer combining analog/mixed-signal verification with software development and automation expertise for robust reusable solutions.
Familiar with AMS verification methodologies and design signoff requirements, capable of developing production-quality automation and regression infrastructure.
Comfortable working across teams (design, CAD, PDK, software) to integrate workflows and support internal and external users in complex semiconductor programs.