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Tier-1 employer and Bangalore metro increase competition despite niche ASIC verification skillset and seniority.
Specialized SoC/ASIC verification skills and protocols create low cross-industry transferability.
Explicit 9-13 years plus mandatory SystemVerilog/UVM, C, and gate-level simulation requirements make screening highly strict.
Lead verification strategy and develop test plans and test benches for complex SoC ASICs.
Collaborate with architects, designers, and verification teams to create C-based tests and meet functional coverage goals.
Run and debug gate-level simulations and generate functional patterns for automated test equipment (ATE).
9-13 years of experience in ASIC digital verification or related field.
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
Deep knowledge of C, SystemVerilog UVM, coverage-driven verification methodology.
Experience with bus protocols (APB, AHB, AXI) and interfaces like PCIe, DP, UART, I2C, SPI.
Experienced in developing and improving UVM-based verification methodologies and advanced testbenches with scoreboards/checkers.
Skilled in scripting languages such as Python, Perl, TCL, BASH for test development and coverage assessment.
Strong expertise in running gate-level and power-aware simulations with excellent debugging skills.