Infra-Sr Staff Design Verification Engineer
Qualcomm Incorporated (company site, opens in a new tab)4+ yrsBengaluruOn-siteDirect career pageEst. 35–70 LPA
Posted on 11 Sept
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Job description
Structured overview of role & requirements
About This Role
- Develop and maintain UVM-based verification environments and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
- Perform block-level and top-level verification activities including functional coverage, assertion-based verification, regression testing, and debug at RTL and gate-level.
- Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure; mentor junior engineers and contribute to improving verification methodologies.
Minimum Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering experience; or Master's with 3+ years; or PhD with 2+ years.
- Strong proficiency in System Verilog, UVM, and verification methodologies.
- Deep understanding of PCIe Gen3-Gen6, CXL 1.1-3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
- Experience using Synopsys/Mentor VIPs and scripting skills in Perl/Python/Tcl for automation.
Ideal Candidate Profile
- 8–12+ years ASIC/Subsystem/SoC verification experience with expertise in high-speed interconnect protocol verification.
- Proven ability to establish verification closure through coverage convergence and assertion-based verification in complex SoC environments.
- Experience collaborating across design, architecture, and validation teams and mentoring junior engineers for verification process improvements.