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Niche compiler/MLIR skillset reduces pool, but Tier-1 employer and metro location increase competition.
Strong hardware-accelerator and ML compiler specialization drives high domain sensitivity.
Mandatory MLIR/IREE/compiler expertise, hardware enablement, and leadership make filtering highly stringent.
Own architecture, design, and development of AI/ML compiler and runtime software targeting RISC-V IP, NPU, and SoC platforms, focusing on efficient execution of AI models for edge devices.
Develop and maintain compiler flows based on IREE and MLIR infrastructure including custom dialects, passes, lowering pipelines, code generation, and integration for hardware accelerators.
Lead cross-functional collaboration with hardware, firmware, validation, and product teams for bringing up AI workloads on simulators, FPGA, emulation, and silicon platforms and deliver runtime optimizations.
3-12 years of hands-on software engineering experience, preferably in compiler, runtime, embedded software, or AI/ML systems.
Strong experience with IREE, LLVM, MLIR compiler infrastructure including developing MLIR dialects and compiler passes.
Proficient in C/C++ and Python scripting for tooling, testing, and automation targeting Linux development and cross-compilation environments.
Location: Pune or Bangalore, India (implied; onsite or hybrid mode not explicitly mentioned).
Experienced in AI compiler/runtime stacks for edge AI and accelerator-backed inference, with deep knowledge of model formats like PyTorch, ONNX, TFLite and MLIR-based model lowering.
Demonstrated ability to provide technical leadership for complex software modules and to work at the intersection of software and hardware by collaborating with architecture and hardware teams.
Hands-on experience with AI hardware accelerators (NPU, DSP, vector/matrix engines) and runtime optimization techniques like quantization, operator fusion, tiling, and memory planning for real-time and low-power AI workloads.