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Tier-1 employer and metro location, but highly specialized ML compiler/runtime reduces applicant density.
Highly domain-specific ML compiler and accelerator expertise limits cross-industry transferability.
Requires deep ML compiler, MLIR/IREE, NPU acceleration, and Linux/C++ experience, making filters stringent.
Architect, design, and develop AI/ML compiler and runtime software for RISC-V based IP, NPU, and SoC platforms targeting efficient edge AI workloads.
Lead development and enhancement of IREE-based compiler flows including MLIR lowering, code generation, runtime integration, and deployment pipelines optimized for custom hardware acceleration.
Collaborate across hardware, architecture, firmware, and product teams to optimize AI model execution performance, provide technical leadership for AI compiler/runtime modules, and support software enablement and deployment.
3-12 years of hands-on experience in software engineering focused on compiler, runtime, embedded software, or AI/ML systems.
Strong proficiency with IREE, LLVM, MLIR infrastructure; experience developing MLIR dialects, compiler passes, and backend integration for custom hardware accelerators.
Proficiency in C/C++ programming and Python scripting; experience with Linux development including cross-compilation, debugging, profiling, and runtime bring-up.
Work Experience Required: 3-12 years of relevant experience. Notice period: Not explicitly mentioned in the JD.
Experienced in AI compiler/runtime stacks for edge AI or accelerator-backed inference with deep understanding of PyTorch, ONNX, TFLite and MLIR-based model lowering.
Skilled at optimizing neural network workloads focusing on quantization, operator fusion, memory planning, and accelerator-aware scheduling for custom NPUs and SoCs.
Proven ability to technically lead complex software modules and collaborate cross-functionally with hardware and product teams, including silicon bring-up and AI software deployment.