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Tier-1 brand but highly specialized PCIe/CXL firmware SQA skills narrow the qualified applicant pool, medium competition.
Specialized PCIe/CXL firmware and automation expertise makes background fit highly sensitive across industries.
Explicit 10–15 years plus mandatory C/C++/Python, protocol, CI/CD and export-control requirements makes filters highly strict.
Manage a team of 3-4 engineers responsible for validation of management subsystems and interconnect technologies including PCIe and CXL.
Develop, review, and maintain production-grade test automation frameworks using Python (Pytest) and C/C++ (GTest), including adding new test cases and debugging failures.
Collaborate cross-functionally to integrate quality processes into CI/CD pipelines using tools like GitHub Actions, GitLab CI, Jenkins, or Azure DevOps, and leverage AI tools for test scenario generation.
10 to 15 years of relevant experience in software design and development using Python and C/C++.
Proven people management skills with experience managing at least 3-4 engineers.
Expert proficiency in Pytest (Python) and C/C++ test frameworks and debugging tools (pdb, GDB, VSCode, PyCharm, CLion).
Experience with CI/CD tools such as GitHub Actions, GitLab CI, Jenkins, or Azure DevOps.
Technical leadership in test automation for memory and interconnect protocols like PCIe and CXL, influencing architectural decisions and driving best practices.
Experienced in combining software development and validation with automation within CI/CD environments to deliver reliable, production-grade test suites.
Skilled at mentoring mid-level and junior engineers and collaborating across teams to define and meet technical requirements.