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Tier-1 employer and metro location drive medium competition despite senior, niche EDA specialization.
Semiconductor DFT/ATPG EDA expertise is highly domain-specific and not easily transferable.
Mandatory 14+ years and specialized DFT/ATPG EDA expertise enforce strict shortlisting.
Identify and define new product features in DFT & ATPG domains, develop product specifications for implementation.
Collaborate with R&D and PV teams to validate features, develop methodologies, flows, and documentation to improve tool usability and quality.
Support existing Innovus hierarchical partition tools and timing closure flow, including benchmarking customer designs and solving complex hierarchical issues.
14+ years of relevant experience in electronic design automation or related domains.
Bachelor's or Master's degree in Electrical Engineering, Electronics & Communication Engineering, or Computer Science.
Experience working with DFT, ATPG domains, and hierarchical timing closure tools (Innovus) as implicit from job responsibilities.
Strong written, verbal, and presentation communication skills; teamwork and collaboration abilities.
Experienced in driving and influencing development of new and existing EDA tools to meet customer and market needs.
Skilled at cross-functional collaboration across R&D, PV, and field teams, including customer engagement.
Operates with creativity in problem-solving, leveraging unconventional solutions to address complex hierarchical design and timing issues.