RISCV Infra System IP DV - Sr Staff Engineer
Qualcomm Incorporated (company site, opens in a new tab)6–15 yrsBengaluruOn-siteDirect career pageEst. 30–60 LPA
Posted on 10 Sept
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Job description
Structured overview of role & requirements
About This Role
- Own and execute IP/Sub System design verification using UVM and System Verilog for RISCV and ARM related architectures.
- Develop comprehensive test plans and cases to ensure code and functional coverage closure, collaborating with system architects and design teams.
- Debug regression failures, work on failure analysis, and support post-silicon bring-up and hardware-software debug activities.
Minimum Requirements
- Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ to 6+ years of Hardware Engineering experience depending on degree level.
- 3 to 15 years of experience in IP/Sub System design verification using UVM, System Verilog, and associated verification components (Checkers, Trackers, Scoreboards, Assertions, Functional Coverage).
- Strong knowledge of bus protocols such as CHI, AHB, AXI, ACE, ACE-Lite and interconnects, and familiarity with ARM/RISCV system architectures including CPU architecture, coherency protocols, and virtualization.
- Proficiency in scripting languages like Python or Perl for automation and knowledge of Gen AI skills is desirable. Location: Bangalore.
Ideal Candidate Profile
- Experienced in collaborating across system architects, design, and emulation teams in a large, global engineering organization.
- Deep understanding of multi-core ARMv8/v9 CPU architecture, RISCV system architecture, memory management, and power management.
- Capable of handling post-silicon bring-up and HW-SW debug, demonstrating ownership of end-to-end verification and debugging of complex SoC IP subsystems.