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Tier-1 brand and metro location but highly specialized SoC/UVM skillset limits applicant pool.
Highly domain-specific semiconductor verification skills have low transferability across industries.
Extensive mandatory SystemVerilog/UVM, SoC verification and domain-specific expertise make filters highly stringent.
Lead end-to-end verification of CPU Co-Processor power management firmware-driven hardware features focusing on power management, reliability, and system readiness.
Architect and develop SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems and AMBA-based system IPs like timers, mailbox, interrupts, and interconnect fabrics.
Own verification planning, test strategy, coverage modeling, functional signoff, and drive cross-functional debugging and root-cause analysis across Firmware, RTL Design, Emulation, and Post-Silicon teams.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Extensive experience in SoC, CPU, or Power-Management verification environments with strong expertise in SystemVerilog/UVM and verification methodologies.
Proven skills in developing NoC transactors, protocol checkers, and verification infrastructure as well as knowledge of AMBA protocols and system-level IPs.
Work Experience Required: 8–12+ years in CPU, GPU, SoC, or complex subsystem verification, with track record in pre-silicon verification methodologies and verification signoff.
Senior-level engineer with demonstrated leadership in verification strategy and execution across geographically distributed teams.
Experienced in building and maintaining automation frameworks, regression infrastructure, and CI/CD workflows in SoC verification.
Strong cross-functional collaborator with background interfacing effectively between Firmware, RTL Design, Emulation, and Post-Silicon teams and mentoring junior engineers.