ASIC Digital Design, Sr Staff Engineer - DDR/LPDDR
Synopsys (company site, opens in a new tab)6+ yrsHyderabadOn-siteDirect career pageEst. 35–60 LPA
Posted on 8 Sept
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Job description
Structured overview of role & requirements
About This Role
- Lead verification teams through full IP verification cycles, including test plan definition, coverage closure, and signoff for DesignWare synthesizable IP cores.
- Develop, maintain, and evolve SystemVerilog/UVM verification environments and testbenches for memory and serial interface protocols including DDR/LPDDR.
- Collaborate with RTL designers and architects to align verification scope, manage regression infrastructure, and drive verification quality and efficiency improvements including AI-assisted flows.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering.
- 6+ years of hands-on verification experience with proven team leadership in IP project delivery.
- Strong expertise in SystemVerilog/UVM testbench development, test plan creation, checkers, assertions, and coverage analysis for DDR/LPDDR and serial interface protocols.
- Work Experience Required: 6+ years in verification including leadership and IP delivery.
Ideal Candidate Profile
- Experienced in end-to-end IP verification with demonstrated success in managing verification signoff and metric closure for high-volume silicon shipping IP.
- Skilled at interacting with design architects and engineers to translate coverage gaps into actionable plans and improvements, capable of working across global teams.
- Proficient in modern verification methodologies, including scalable test environments and AI-assisted verification tool usage, with focus on quality and efficiency.