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Tier-1 employer and metro location increase competition, but niche EDA/physical-design specialization limits candidate pool.
Highly specialized SoC physical design skills make cross-industry transfers difficult.
Explicit 7+ years requirement plus niche EDA tools and methodology mandate tight filtering.
Develop and maintain Physical Design flows including Floorplanning, PnR, CTS, Routing, IR/EM, and Signoff for complex SoC projects.
Build automation and infrastructure using Tcl, Python, Perl, and Shell scripting to enhance design efficiency and turnaround time.
Lead methodology improvements and collaborate with PD, STA, CAD teams, and EDA vendors to deploy new tools and scalable solutions across advanced technology nodes.
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
7+ years of experience in Physical Design CAD, Methodology, or Design Automation.
Strong expertise in Physical Design implementation and signoff flows with proficiency in Tcl, Python, Perl, and Linux.
Experience with Cadence and/or Synopsys EDA tools.
Experienced in handling complex SoC Physical Design CAD methodologies and automation at advanced nodes (7nm and below).
Demonstrates strong technical leadership and mentoring capabilities within cross-functional teams.
Skilled in improving design productivity through flow validation, regression automation, and collaboration with EDA vendors.