Staff Engineer – STA Methodology/CAD
Qualcomm Incorporated (company site, opens in a new tab)7+ yrsBengaluruOn-siteDirect career pageEst. 40–65 LPA
Posted on 9 Sept
Reach people at Qualcomm Incorporated
People at this company you can reach
Log in to see who works here
Create a free account or log in to see the people at Qualcomm Incorporated you could write to:
- Recruiters & HR
- People in this function
- Work addresses
Your match
Against your primary resume
Log in to see your match score
Create a free account or log in to unlock your CV match score across:
- Role fit
- Experience
- Industry relevance
Protocol Intelligence
How competitive this role is
Competition
Background fit
Strictness
Log in to see why each signal reads the way it does.
Job description
Structured overview of role & requirements
About This Role
- Develop, improve, and drive next-generation Static Timing Analysis (STA) methodologies for block, subsystem, and full-chip SoC designs.
- Own timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and timing closure reporting and quality metrics.
- Lead development of automation infrastructure using Tcl/Python/Perl and collaborate with RTL, Synthesis, Physical Design, DFT, and CAD teams for timing convergence and methodology adoption.
Minimum Requirements
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
- 7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.
- Proficiency with Synopsys PrimeTime or Cadence Tempus and strong scripting skills in Tcl and Python.
- Strong knowledge of Static Timing Analysis, MMMC timing signoff, timing constraints (SDC), setup/hold closure, SOCV/AOCV derates, and ECO techniques.
Ideal Candidate Profile
- Experienced in developing and scaling STA methodologies for advanced technology nodes (7nm and below) and complex SoC designs.
- Demonstrated capability in driving methodology improvements that are adopted across multiple programs with cross-functional collaboration.
- Proficient with timing automation frameworks, dashboards, AI/ML-driven timing optimization, and possesses technical leadership skills to mentor junior engineers.