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Strong Tier-1 employer and metro location but niche STA specialization limits applicant pool.
Highly specialized STA/CAD methodology skills and EDA tool experience are not easily transferable across industries.
Explicit 7+ years requirement, mandatory STA/CAD tool expertise, and scripting skills enforce strict filters.
Develop, improve, and drive next-generation Static Timing Analysis (STA) methodologies for block, subsystem, and full-chip SoC designs.
Own timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and timing closure reporting and quality metrics.
Lead development of automation infrastructure using Tcl/Python/Perl and collaborate with RTL, Synthesis, Physical Design, DFT, and CAD teams for timing convergence and methodology adoption.
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.
Proficiency with Synopsys PrimeTime or Cadence Tempus and strong scripting skills in Tcl and Python.
Strong knowledge of Static Timing Analysis, MMMC timing signoff, timing constraints (SDC), setup/hold closure, SOCV/AOCV derates, and ECO techniques.
Experienced in developing and scaling STA methodologies for advanced technology nodes (7nm and below) and complex SoC designs.
Demonstrated capability in driving methodology improvements that are adopted across multiple programs with cross-functional collaboration.
Proficient with timing automation frameworks, dashboards, AI/ML-driven timing optimization, and possesses technical leadership skills to mentor junior engineers.